Design of a 60 GHz LNA with 20 dB gain and 12 GHz BW in 65 nm LP CMOS

A 60 GHz three-stages broadband Low Noise Amplifier (LNA) is designed in a 65 nm LP CMOS process. By controlling the reflection coefficients of components within the targeted frequency band, the trade-off among gain, noise figure (NF) and power consumption is realized. Simulation results show that the transducer gain is greater than 20 dB, and the noise figure is less than 6 dB, with a power consumption of 34.22 mW from a 1.2 V supply. The in-band ripple is less than 1 dB from 57 GHz to 66 GHz, and the 3-dB bandwidth is from 55 GHz to 67 GHz.