Low Resistance Electrical Layer Formation: A Simulation Study of Diffusive Rapid Thermal Process on Implanted Dopant Species for Electronics Active Devices

A simple and economical spin-on-dopants simulation technique for ultra thin layer formation is presented; the Ultra thin for the purpose of shallow junction formation in large scaled integrated technology is one of the most challenging in device fabrication. Low energy ion implantation is the most widely used technique at present to form ultra shallow junction but this method has some limitations such as silicon surface damage, however, many attempt have been made to overcome this but it seems difficult to do away with this limitation. An ultra high shallow junction formation of <; 20 nm was proposed through thermal diffusion from spin-on dopants into silicon, the study presented a determination of the junction depth and the sheet resistance of the shallow junction in order to fulfill the standard semiconductor device design requirements. Ultra shallow junction which is defined to be less than 20 nm in depth was obtained through this simulation using very simple and easy spin-on dopants technique.