Applying Virtual Test principles to digital test program development

Simulation model development and test program integration can account for over half the effort spent on digital TPS development. Digital test development in a Virtual Test environment can result in substantial TPS cost reductions through a combination of VHDL device model reuse and ATE environment simulation. Technology developed under the VTest contract sponsored by the U.S. Air Force Wright Laboratory Manufacturing Technology Directorate enables fault simulation of devices supported by VITAL libraries, thereby extending the use of VHDL into test program generation. Simulation driven VTest methodologies enable development of digital test programs completely off-line and with the ability to target virtually any digital ATE.