A new architecture of signature analyzers for multiple-output circuits

The paper presents an architecture for multiple input signature analyzers. The proposed signature analyzer with H/spl delta/ inputs is designed by parallelizing a GLFSR(/spl delta/,m), where /spl delta/ is the number of input signals and m is the number of stages in the feedback shift register. The GLFSR, developed by D.K. Pradhan and S. Gupta (1991), is a general framework for representing LFSR based signature analyzers. The parallelization technique described in the paper can be applied to any kind of GLFSR signature analyzer, e.g., SISRs, MISRs, multiple MISRs and MLFSRs. It is shown that a proposed signature analyzer with H/spl delta/ inputs requires less complex hardware than either single GLFSR(H/spl delta/,m)s or parallel construction H original GLFSR(/spl delta/,m)s. It is also shown that the proposed parallelization technique can be applied to a test pattern generator in BIST, since the GLFSR is also used to generate patterns for a CUT. The proposed technique would be practical for testing CUTs with a large number of input and output sequences, since the test circuit occupies a smaller area on the LSI chip than conventional test circuits.