A study of communication performance in the infrastructure of cluster-based MPSoC

In an era of multi-core and even many-core processors, with the increase of the number of cores integrated on a single-chip, how to organize these cores efficiently is becoming the key issue to make multi-processor systems optimal. The infrastructure of cluster-based multi-processor system-on-chip (MPSoC) is promising, and welcomed because of its hierarchy and scalability. However, how to configure the number of processing cores in each cluster has so far proved inconclusive. This paper shows the relationship between different processing core number configuration in each cluster and multi-processor system communication performance, and a C++-based cycle-accurate simulation model has established. The simulation model can be configured, and has fast simulation. When the total number of processing cores is fixed, changed the configuration of processing core numbers in each cluster, could get different system communication performance. Comparison of communication performance under different configurations to obtain the best, it may provide guidance to configure core numbers in the infrastructure of cluster-based MPSoC to gain a high communication performance.