Energy and performance tradeoffs for matrix multiplication on multicore machines

In this paper, we propose a general methodology for energy estimation of bus-based multi-core processors assuming that DVS can be used for both buses and cores. Our formulation can provide tradeoffs between DVS setting for buses and cores. We examine this methodology using various parallel matrix multiplication algorithms that are suitable for shared memory multicore machines with L1 and L2 caches. Our simulation results show that the simultaneously changing the voltage of buses along with cores can result in 10 - 20% reduction in the overall energy requirements as compared to only changing the core voltages. This is under the assumption that sufficient slack is available for DVS to be able to work at lower voltages to save energy. The methods proposed in this paper demonstrate the usefulness of multiple element optimization in multicore architectures. The experiments show that a good understanding of the overall tradeoffs between the effect of these elements in the overall performance and energy requirements can lead to improved results in the energy requirements.