A novel design concept for high density hybrid CMOS-nanomagnetic circuits

In this paper we have presented a novel design concept in hybrid CMOS-Nanomagnetic logic architecture and have shown it for a 2-input XOR. This paradigm is based on Shannon's expansion theorem and distributes the role of logic computation between the spin transfer torque magnetic tunnel junctions (STT-MTJs) and the CMOS metal lines. A 81.25% reduction in cell count and more than 75% reduction in energy consumption is achieved with this design strategy. The concept can be extended to any n-input XOR and other suitable logic functions.