Synchronization algorithm and FPGA implementation for Transmit-Reference UWB receiver

This paper proposes a practical synchronization algorithm for Transmit-Reference UWB receiver which uses sliding window and supports flexible sampling rates. Additionally, a Simulink model and implementation of synchronization algorithm in receiver by hardware description language (HDL) is also developed using model-based design. Finally, we assess impact of signal-noise-rate (SNR), number of bits quantization and sampling rate on bit-error-rate (BER).