A low cost EEPROM design for passive RFID tags

This paper presents an EEPROM ultra low cost design for RFID applications. Two different read principles of the non-volatile memory are observed: the dynamic reading and the low current static reading. We designed Dickson and latched charge-pump circuits with active and reverse-biased diode regulation. An EEPROM dissipate 1.5μW/15μW for dynamic/static 32-bit reading operations and 50μW for writing operations with the latched charge-pump circuit. A 640-bit EEPROM is fabricated in 2-poly 4-metal 0.18 μm CMOS process. The EEPROM core area is only 0.03 mm², the area of EEPROM high-voltage programming controller is 0.01 mm²/0.025mm² for latched/Dickson architectures.