GC-ARM: Garbage Collection-Aware RAM Management for Flash Based Solid State Drives

Previous on-board RAM management algorithms of SSD are oblivious of garbage collection (GC) efficiency in that they fail to analyze the performance degradation from the perspective of GC efficiency and thus unable to find the true culprit. For some workloads that do not generate enough invalid data, these approaches will suffer from severe performance degradation. Further, the existing write-buffer component in SSD is by and large oblivious of how FTL works in SSD, unable to minimize the address translation overhead. The GC efficiency and FTL obliviousness of SSD RAM buffer management can result in significantly increased GC-induced and address-translation-induced write traffic to the flash memory, which is very harmful to both performance and endurance. To address these performance and endurance issues of SSD, we propose GC-ARM, an SSD RAM management scheme consisting of a write buffer component and an FTL component. On the one hand, the write-buffer design of GC-ARM can improve the garbage collection efficiency by evaluating the benefits of different destaging approaches. On the other hand, the FTL component is designed to interact with the write-buffer component to reduce the address translation overhead. Moreover, GC-ARM optimizes the size ratio of RAM space allocated to the write buffer and the FTL's mapping table based on the varying randomness of workloads. Extensive trace-driven evaluation results show that GC-ARM consistently outperforms the state-of-the-art FTL and buffer management schemes in terms of the number of erasures, average response time, garbage collection efficiency and write traffic reduction.