An FPGA-based intellectual property protection method at physical design level

An FPGA-based intellectual property protection method at physical design level is presented for ownership identification in IP reuse. The method uses the special physical structure of FPGA for watermark insertion and adds corresponding checkout mechanism in functional circuit for strengthening robustness. Watermark extractor is designed for extracting watermark by analyzing bitstream. The experimental results on Xilinx Virtex II Pro XC2VP4 shows, the presented method has less resource and timing overhead.