Simulating the impact of poly-CD wafer-level and die-level variation on circuit performance

In this paper, we present a methodology for simulating the impact of wafer-level (within-wafer) and die-level (within-die) variation on circuit performance. For a sample 0.25 /spl mu/m 64/spl times/8 SRAM layout, the impact of both die-level and wafer-level poly-CD variation as measured through signal skew and delay is shown to be significant.