Power compiler: a gate-level power optimization and synthesis system

Commercial synthesis tools traditionally perform timing and area optimization, however power reduction is rapidly becoming an equally important design goal. Recent research in power optimization has produced several algorithms, however, each algorithm is focused on one aspect of the whole power equation. This paper describes a commercial tool capable of optimizing power at the gate-level in addition to performing area and timing optimization. A power analysis engine that models all aspects of power consumption is integrated into the optimization tool so that all aspects of power are considered. Experimental results show an average 11.46% reduction on industrial circuits with a peak reduction of 66.62%. All delay constraints are met and an average 9.41% increase in area is observed.