Built-in self test for content addressable memories

A new parallel test algorithm and a Built-in Self Test (BIST) architecture for an efficient testing of various types of functional faults in Content Addressable Memories (CAMs) are developed. In test mode, the read operation is replaced by one parallel content addressable search operation and the writing operation is performed parallel with small peripheral circuit modifications. The results show that an efficient and practical testing with very low complexity and area overhead can be achieved.