Implementation aspects of lattice bilinear digital ladder filters

Lattice bilinear digital ladder filters (BDLF) were introduced in a previous paper. Here, some results regarding hardware implementation of lattice BDLFs are presented. Both direct implementation of the signal flow graph (SFG) and state-space implementation are considered. At the most, a critical path of two multipliers and four adders is obtained, enabling sampling rates up to 40 and 20 MHz, for the state-space and SFG implementations, respectively. This combined with the low sensitivity inherent with the BDLF structure allowing implementation with short word-length multipliers-clearly indicates that lattice BDLFs are viable contenders to circulator lattice wave digital filters for high-speed applications.