A current-to-voltage integrator using area-efficient correlated double sampling technique

This paper provides an area-efficient, low power and high precision current-to-voltage integrator for photocurrent measuring by using correlated double sampling. A novel CDS scheme is devised by using an interstage capacitor instead of the large error store capacitor to reduce kT/C noise. An integrator prototype with the proposed technique is fabricated using 0.8-μm 2P2M CMOS process for demonstration. The measurement results show that the output noise is 95μV and 59μV with the integration capacitor 4pF and 32pF, respectively, both for a 33pF photodiode parasitic capacitor. For a 3V output swing at 5V supply, the resolution is about 15bit.