3D-Scalable Adaptive Scan (3D-SAS)

Performance requirements and interconnect bottlenecks associated with technology scaling have led to the development of 3D stacked ICs (3D-SICs) based on through-silicon vias (TSVs). Testing of 3D-SICs is challenging due to severely limited physical access. In a limited access situation, test compression offers a promising solution to the problem of testing 3D ICs. Scalable Adaptive Scan (SAS) requires a very narrow scan interface. This paper integrates SAS with known core test-wrapper designs and emerging die wrapper methods to provide an effective solution to the problem of testing 3D-SICs.