Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer

For the last few decades semiconductor industry has been following Moore Law effectively, which has resulted in significant miniaturization of transistors and on chip logic circuitry. Below the 28nm node, as design complexity of the IC (Integrated Circuits) increases, cost and risk associated with these designs are becoming prohibitive for many companies. Three dimensions (3D) die stacking methodology offers unique advantages of low power and high bandwidth per watt without increasing the cost significantly. For FPGAs (Field Programmable Gate Array), stacked silicon integration (SSI) technology offers a cost effective solution to build large die with very high logic cell count. In order to create a larger FPGA, four different 28nm FPGA die are connected to each other through a 65nm passive silicon interposer. The FPGA die are connected to interposer through micro-bumps (ubumps). This paper describes the technical challenges associated with 3D integration of 100um thin interposer and FPGA die on to a package and stacked die package reliability. The assembly test vehicle was comprised of four 28nm chips mounted side by side on a 25 mm × 31 mm 100um thick interposer with thousands of micro-bumps at 45um pitch. This top die and interposer stack was assembled on a 35mm × 35mm and 45mm × 45mm package with 180um pitch C4 bumps. Several assembly experiments were performed to compare performance of mass reflow assembly and thermo compression bonding assembly to join top FPGA die with ubumps. Assembly yield and reliability were used as two main criteria in deciding the best assembly process. Micro-bump resistance was monitored by Through Silicon Via (TSV) chains, Kelvin bump structure and daisy chains in order to check interconnect integrity after assembly and during reliability testing. After assembly evaluations, separate underfill screening design of experiment (DOE) was performed to choose the best underfill candidates for reliability evaluations. Reliability evaluations were performed with best underfill candidates and parts were subjected to L4 preconditioning and -55°C to 125°C thermal cycling. Parts were subjected to extended thermal cycling, i.e. beyond 1000 cycles, to understand the other possible failure modes. Assembly evaluations showed that the choice of the assembly process was strongly dependent on the die size, interposer design and interposer process. Choice of flux also affected the ubump assembly yield and underfill flow. Underfilling experiments confirmed that optimization of underfill process required optimization of dispense pattern, ubump parameters. Reliability evaluations showed that the reliability was affected by choice of underfill, interposer cleaning, and die thickness/package structure. One of the common failure modes was delamination between interposer and C4 underfill.