Design of PLL For TD-SCDMA system

Error Vector Magnitude (EVM) is a key parameter for modern wireless communication such as TD-SCDMA and WCDMA. In TD-SCDMA system, there are many factors affecting the result of EVM and the phase noise of local oscillator (LO) is the most important one, so how to implement a phase-lock loop (PLL) design based on the EVM specification is challenging for radio designers. In this paper, we analyzed the relationship between EVM (Error Vector Magnitude) and phase noise of PLL based on the structure of the TD-SCDMA system firstly. Secondly, A PLL simulation program which combined with the EVM simulation is written with ADS (Advanced Design System). Finally, as a practical application, the paper introduced a PLL circuit design for the TD-SCDMA system.