Efficient implementation of channel coding and interleaver for Digital Video Broadcasting (DVB-T2) on FPGA

This paper presents the implementation of a single FPGA intellectual property (IP) core for channel coding and interleaving used in Digital Video Broadcasting, second generation (DVB-T2). DVB-T2 is the extension of the television standard DVB-T, issued by the consortium DVB, and is devised for the broadcast transmission of digital terrestrial television. The higher offered bit rate, with respect to its predecessor DVB-T, makes it a suited system for carrying high definition TV (HDTV) signals on the terrestrial TV channel. In this paper we specifically target the version suitable for China Multimedia Mobile Broadcast (CMMB) standard that works on the 2,635 to 2,660 MHz frequency band to provide 25 video and 30 audio channels. The main contribution is the design and development of forward error correction (FEC) part for mobile multimedia broadcast system, its estimation of power dissipation and optimization. The FEC part includes Reed Solomon (RS) encoder and byte interleaver, low density parity check (LDPC) encoder and bit interleaver. All these sub-modules have been implemented and integrated for the target device Stratix III E (EP3SE50F780C4N). The design has been coded in verilog-HDL and synthesized using Quartus II 8.1 software tool. PowerPlay Power Analyzer tool provided by Altera with Quartus II software has been used for the estimation of power dissipation. Stratix III logic array block level programmable power technology and clock gating technique has been used for power optimization.