Scalable front-end digital signal processing for a phased array radar demonstrator

The European Space Agency (ESA) is in the process to develop a ground-based space surveillance radar for its involvement in the Space Situational Awareness (SSA) Preparatory Programme [1]. The radar is intended to systematically survey and track all objects above an altitude dependant size threshold in the low Earth orbit and, based on these data, maintain a catalogue with physical and orbital information. Phased array radar demonstrators are currently being developed by industry in cooperation with ESA. These radars are precursor systems and will assist in the definition of the final SSA radar architecture. In support of these developments a small-scale phased array radar demonstrator is being developed at the European Space Operations Centre (ESOC). The system is not intended to detect space debris objects but to implement the general functionality of its large-scale counterparts. This paper describes the mini-radar design and implementation. Furthermore, measurement results showing the performance of the system are presented. In order to cope with the high data processing throughput demand at the multi-channel receiver, an efficient field-programmable gate array (FPGA) implementation is adopted for the front-end pre-processing and digital beam-forming. As the computational burden for the forthcoming SSA phased array radar architecture including several hundreds or thousands of receiver elements is very high, an estimation of computational complexity for different signal processing building blocks is presented here.