Low power optimization for a 40nm RFCMOS wireless connectivity chip

In this paper we present the power optimization of a GNSS, Bluetooth, FM radio combo SoC for smartphones and tablet devices. The optimization ranges from architectural level, clock management level and RTL level. The techniques of power state and power control, clock gating, clock distribution, operand isolation and logic grouping have been tailored to the specific needs of wireless combo SoC. The techniques and optimization has been proven on fully functional 40nm RFCMOS silicon and shows up to 20% power reduction vs. non-optimized version.