Ultra low voltage ΔΣ modulation using biased inverters in 130nm CMOS

The design challenges of an ultra low voltage ΔΣ modulator are discussed, which encompasses a switched capacitor technique for efficient biasing of inverter-based integrators, an ultra low voltage comparator as well as efficient on-chip bias current generation and clock boosting for fast switching transients. All building blocks run at a supply voltage of only 250 mV while providing 61 dB SNDR in 10 kHz bandwidth at a total power consumption of 7.5 μW.