A CMOS power amplifier for 5.8GHz DSRC application

Based on TSMC 0.18-μm CMOS process, a 5.8-GHz CMOS power amplifier for DSRC application is investigated in this paper. The proposed power amplifier is consisted of two stages which are followed by input, output and inter-stage matching networks. Capacitance compensation technique is employed to improve the linearity of the output stage power amplifier. Simulation results show that the designed power amplifier with low voltage operation of 1.8 V can achieve linear power gain of 16.9 dB, 1 dB compression power output of 17.6 dBm, third order inter-modulation distortion (IMD3) of -43 dBc at the output power of 10 dBm, which has about 8 dB improvement compared with the structure without the capacitance compensation technique.