FPGA implementation of chaotic pseudo-random bit generators

We present recent results of our studies on the FPGA implementation of pseudo-random bit generators (PRBGs) based on a chaotic behavior of nonlinear systems. A number of different PRBG architectures have been considered, including logistic mapping, Hénon mapping, and frequency dependent negative resistor (FDNR). All versions of PRBGs have been implemented in five FPGA families of devices from Xilinx (Spartan 3 and 6, Virtex 4, 5, and 6). We present detailed comparison of FPGA resources required for PRBG implementation and evaluation of maximum operating frequencies. The pseudo-random bit generators presented in this paper can be used for key generation in stream ciphers in secure, real-time transmission of digital signals.