Possibilities for FIR filter kernel code optimization for DSP processors

Digital signal processing (DSP) is one of the fastest growing fields in modern electronics. Today we meet DSP processors in numerous application areas, such as communication, electro-medicine, multimedia, etc. One of the crucial problem which have to be solved in these applications relate to filtering. During this it is of paramount importance to create efficient algorithms. In this paper, creation of time efficient algorithms is considered. To this end, several FIR filtering algorithms were created in HLL C and ASM, and optimized in respect to execution time. For optimization, we used techniques such as loop unrolling, software pipelining, code reordering, etc. All proposed code optimization techniques are implemented on Texas Instruments (TI) TMS320C6713 DSP processor and Code Composer Studio as software tool. For performance evaluation, speedup factor was used. The obtained results show that speedup is within a range from 1.97 up to 5.36.