The Effect of Gate Length on Channel Strain of Recessed Source/Drain Si1-xCx

In this study, we experimentally evaluated the effects of scaling on the channel strain in terms of gate lengths. We used transistor arrays incorporating Si1-xCx as a stressor with systematically varying gate and source/drain lengths, and employed the NBD method to measure the channel strain. We also carried out simulation to check the validity of the NBD data.