High-κ Gate Dielectrics for Ge CMOS and Related Memory Devices

To reach future low power operation at ≤0.5 V, high mobility InGaAs nMOS and Ge pMOS were proposed at sub-14 nm nodes. However, the integration of InGaAs on Si faces difficult challenges of the large 8% lattice-mismatch, high dislocation densities, and antiphase domain boundaries. Although the defect-free Ge-on-Insulator (GOI) [1], ultra-thin-body (UTB) InGaAs IIIV-on-Insulator (IIIVOI) [2] on Si, and selective GOI [3] were reported by us, it is still different to reach IIIVOI and GOI side-by-side for high mobility InGaAs-Ge CMOS. On the other hand, the Ge has both higher electron and hole mobility than Si for all Ge CMOS. The GOI pMOS on Si has achieved 2.6 times higher hole mobility than universal SiO2/Si value at a medium effective field (Eeff) of 0.5 MV/cm and a small equivalent-oxidethickness (EOT) of 1.4 nm. Although the GeO2/Ge nMOS reported high peak mobility at small Eeff, fast mobility degradation with increasing Eeff and decreasing EOT were found.