Harmonic free Delay Locked Loop having low jitter with wide-range operations

A Delay Locked Loops (DLL) suffers from harmonic locking problem over wide-range frequency operation. Phase selection circuit plays an important in DLL. It is used not only to widen the operating frequency range and eliminating harmonic locking problems but also for fast locking mechanism. Normal phase selection circuit has the problem of generating more delayed feedback clock due to which false locking occurs. The approach presented in this paper uses a Modified Phase Selection circuit to automatically decide the number of delay cells that can be used, in-order to operate DLL over wide frequency range and completely remove the false locking problem. The circuit is simulated in Cadence Spectre using TSMC 180nm CMOS technology and 1.8V power supply voltage. The operating frequency ranges from 70MHz to 800MHz and temperature ranges from −40° C to 120° C. The DLL consumes maximum power of 6.2mW at 800MHz with maximum peak-to-peak jitter of 7ps at 70MHz.