High-speed VLSI design of the LZ-based data compression

In this paper, a high-speed VLSI design of the LZ-based data compression is presented. The proposed block processing architecture provides 100 percent hardware utilization and a shorter cycle time for searching the maximum matching strings. A systematic method to find the sharing substructure among the block structures is also proposed. With this systematic method, it can shrink the final area requirement on a single chip for on-line data compression. Hence, the proposed design is more area-efficient than the previous systolic designs.