Low voltage swing circuits for low dissipation busses

Power reduction is one of the most important issues of modern VLSI design. Many analyses show that a larger quantity of power is dissipated for the communication, both inside and outside the chip. Different methodologies have been proposed to reduce such power dissipation. In this paper we consider the approach based on reduction of the voltage. In the literature this approach is based on interface circuits that make use of sophisticated technology. Moreover, these circuits are quite complex. Our efforts are devoted to developing a solution based on quite simple interface circuits implemented in conventional CMOS technology. In this paper we review the interface circuits already proposed by the authors and discuss the measurement results of a test chip. Starting from the drawbacks highlighted by these measurements, we propose new circuits based on a new technique of voltage swing reduction and present a preliminary simulation.