Formal Design of Multiple-Valued Arithmetic Algorithms over Galois Fields and Its Application to Cryptographic Processor

This paper presents a formal description of multiple-valued arithmetic algorithms over Galois Fields (GFs). Our graph-based method can be applied to any multiple-valued arithmetic circuit over GF(2^m). The proposed circuit description is formally verified by formula manipulation based on polynomial reduction using Groebner basis. In this paper, we first present the graph representation and its extension. We also present an application of the proposed method to cryptographic processor consisting of GF(2^m) arithmetic circuits. The target architecture considered here is a round-per-cycle loop architecture commonly used in the design of cryptographic processors. The proposed approach successfully describes the 128-bit data path and verifies it within 4 minutes.