Peak wake-up current estimation at gate-level with standard library information

In power gating designs, it is important to estimate the peak wake-up current at the design stages to avoid possible power issues.In this paper, an analytical approach is proposed toestimate the peak wake-up current of a given wake-up input pattern at gate level. The required information of the proposed approach can be directly obtained from existing library information without extra characterization, which can be easily inserted into existing EDA flow with little overhead.The extra effects of power switches on the current waveformsare also considered in the proposed approach, which significantly improve the estimation accuracy as demonstrated in the experiments.