Design and Implementation of a High Efficiency CMOS Power Amplifier for Wireless Communication at 2.45 GHz

This paper presents the design and evaluation of a high efficiency power amplifier with high voltage capability. And power amplifier based on two-stage topology at frequency of 2.4 GHz ISM band. The optimization of source and load impedance for the proposed power amplifier is determined using smith chart or tuning system. Power output spectrum is designed including harmonic resonators up to 3rd harmonic. This power amplifier provides a excellent performance. In which we use the two-stage topology. The simulated power amplifier achieved maximum power added efficiency (PAE) of 34 %. The total Gain (S21) is 23.4 dB. And input return loss and output return loss is 13dB and 11 dB respectively. The proposed method is addressed to optimize power efficiency while maintaining good input and output matching. The design simulation process is using Advance Design System (ADS) software.