Leveraging both Data Cache and Scratchpad Memory through Synergetic Data Allocation

Although a data cache provides fast access latency, it degrades the timing predictability of real-time embedded systems due to misses which are difficult to predict. Scratch pad memory is accessed as fast as a data cache, but does not suffer from unpredicted misses thanks to its software-controlled mechanism. This study presents how scratch pad memory reduces data cache pollution and misses for preemptive real-time embedded systems, so that both of the fast memory subsystems can work together with synergy. First, by classifying data cache misses into intrinsic misses and interference misses we reveal previously hidden characteristics of the interactions between data in the cache. Second, we suggest a heuristic method of data allocation to scratch pad memory using the new perspective, which reduces the cache pollution and finally improve the cache performance. Third, we examine these concepts with several tasks running on a real hardware platform and a preemptive real-time operating system. In addition, we perform a supplementary case study which shows how sensitive the data cache is to small changes of data memory layout and its dynamic contents. Our proposed scheme guides us through the synergetic process by using scratch pad memory beyond the sensitive data cache. In our experiments, the proposed data allocation scheme significantly reduces inter-task cache pollution as well as the intrinsic cache misses of the tasks themselves.