Graph modeling for Static Timing Analysis at transistor level in nano-scale CMOS circuits

As a result of the evolution to nano-technology, the demand for accurate Static Timing Analysis (STA) at transistor level for high speed/high performance digital integrated circuits is increased. Despite the existence of many research attempts to resolve the timing analysis problems, (STA) remains the best solution because of the extremely fast run time and accuracy. The accurate modeling for highly resistive interconnects, nonlinear driver and receiver that effects in crosstalk noise analysis require accurate transistor level model. This model provides solution for false paths problem that is found in classic gate or arc models. In this paper, a new graph model is proposed at transistor level to describe the behavior of CMOS circuits. This model is dealing with CMOS circuit as a pool of transistors regardless its positions in the gates to overcome problem of false paths. By this model, accurate circuit timing analysis is estimated based on BSIM4 equations. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested circuits.