Design and implementation of IEEE 802.16 baseband system on FPGA

In this paper, a physical-layer baseband modem is discussed based on IEEE 802.16 protocol. It is implemented on Xilinx FPGA and tested correctly in loop-mode. After channel coding, a bit stream goes through constellation mapper, pilot inserting, OFDM(Orthogonal Frequency Division Multiplexing) modulation, PAPR(Peak to Average Power Ratio) reduction and framing module to become 7 symbols in IQ parallel form prepared for RF(Radio Frequency) front end. On condition of loop-mode, these symbols become back to serial bit stream via synchronization, channel estimation, OFDM demodulation, pilot removing and constellation demapper in receiver part. In practice, the entire loop-mode system takes about 120us when clock rate is 40Mhz. As a consequence, the baseband system delay is much lower in order to satisfy the demands for high rate data processing in broadband communication.