Implementation and analysis of power clock generation method for adiabetic circuits

We present a sinusoidal single phase power clock generation method for low energy (adiabatic) circuits. In this paper radio frequency resonant DC-AC converter is proposed as power clock generator. We have also obtained square wave from RC oscillator consisting of cascaded NOT gates. This square wave and its inverted and delayed version are used as gate-drive signals for MOSFET switches those are used in the LC resonant circuit. A 2:1 MUX, implemented in Pass-transistor Adiabatic Logic (PAL) style, is operated from this power clock to illustrate power saving. It is observed that power dissipation of PAL 2:1 MUX is about 26 times lesser than that of conventional CMOS 2:1 MUX. If for 2:1 MUX, PAL logic is implemented in place of conventional CMOS logic, power saving per MUX that is achieved is about 96%. Also power dissipated in Power Clock is found to be equivalent to power dissipated in five CMOS 2:1 MUXs. 0.35μm technology is used for obtaining simulation results.