An fpga implementation of Low Density Parity-Check CodeS construction & decoding

This paper presents implementation of Low Density Parity-Check (LDPC) Codes on FPGA Platform. LDPC codes has been implemented by writing Hardware Description Language (Verilog) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip. Repeat-Accumulation LDPC codes are also constructed. Codewords have been constructed & simulated for different rates such as 1/2 rate, 1/3 rate, 1/4 rate. The iterative decoding algorithms such as Belief Propagation (BP) and Bit-Flipping has been implemented and desired simulation results were obtained using three different coding (C, Verilog-HDL, MATlab (Simulink)) styles. Synthesis has been done for LDPC codes Construction & Bit-flipping decoding using Leonardo-Spectrum and Xilinx-ISE Project Navigator. This code is useful for large and small length of block codes. So this is flexible to use for any length of code word (or) data word and also for any rate of code word. So the usage of this code leads to high performance. The above decoding algorithms can recover the original codeword in the face of large amounts of noise.