A 3D IC designs partitioning algorithm with power consideration

We present an effective algorithm to partition a circuit into k layers under power density constraints for 3D IC designs. Our algorithm utilizes a multilevel structure and a successive 3D aware two-way partition method to minimize the number of signal TS Vs and area overhead. A layer swapping technique is used to improve total number of signal TSVs and power TSVs. Finally, a zero-gain cell move technique is used to refine the area overhead. Our test cases are 4 industrial circuits provided in the IC/CAD 2011 contest in Taiwan [1]. Experimental results show that our results are better than those of all teams in the contest. In addition, we study the impact on signal TSVs of an extended hMetics method, simultaneous k-way partition, and successive two-way partition for k layer 3D ICs. The results show that the successive two-way partition method is superior to the other methods both in number of TSVs and run time.