Power Delivery for 3-D Chip Stacks: Physical Modeling and Design Implication

3-D integration creates vast opportunities to improve performance and the level of integration in nanoelectronic systems. However, 3-D integration presents many challenges for power delivery network design due to larger supply currents and longer power delivery paths compared to 2-D systems. In this paper, an analytical physical model is derived to incorporate the impact of 3-D integration on power supply noise. The model has less than 4% error compared to SPICE simulations. Based on the model, design guidelines and opportunities for reducing power supply noise, such as inserting “decap” die and through-vias, are discussed in this paper.