A trench isolation process for BiCMOS circuits

A new isolation process using 1 /spl mu/m deep trench is developed for BiCMOS circuits. Well behaved MOSFETs and NPN devices with excellent parasitic performance were achieved. Low leakage diodes with butted junctions were demonstrated by inclusion of an oxidation barrier in the trench liner and utilizing a GeO/sub 2/ doped oxide with matched thermal coefficient of expansion to the silicon substrate for trench fill. Planarity for arbitrary width isolation was obtained by using oxide RIE followed by chemical-mechanical polishing.