CMOS latchup characterization for LDMOS/LIGBT power integrated circuits

This paper presents a unique characterization technique for CMOS latchup in power integrated circuits. To this purpose, test structures are designed and implemented using a 2-/spl mu/m twin-well CMOS/LDMOS/LIGBT high voltage process. Lumped element models are used to study the latching mechanism. Crosstalk between LDMOS and CMOS as well as between LIGBT and CMOS is investigated. It is shown that great care should be taken when designing power integrated circuits since CMOS latchup is initiated even at low operating current of the power devices.