A 7-bit 16-MS/s low-power CMOS pipeline ADC

This paper describes a 7-bit 16MS/s CMOS pipeline ADC for the application of ZigBee receiver. A 2.5-bit/stage Multiplying DAC (MDAC) is designed to realize the pipeline ADC. Sample-and-hold amplifier (SHA)-less and operational transconductance amplifier (OTA)-sharing technique is adopted to save power dissipation. Dynamic comparator can be chosen to reduce the power dissipation. Designed in a TSMC 0.18µm CMOS process, a power dissipation of only 3.7 mW from a 1.8-V supply is achieved. The area of ADC core is 0.65mm×0.38mm, the post-simulation shows that SNDR and SFDR are 40.9dB and 48.6dB, when sampling 3.015625MHz sinusoid input signal at 16MHz sampling clock.