Camera head of the DSSC X-ray imager

A description of the camera-head electronics of the DSSC mega-pixel X-ray imager is given. The integration of 32 sensor chips, 256 ASICs, 112 PCBs, and 16 flex cables in the space of 241mm × 251mm × 224mm underlines its compactness. Prototypes of subassemblies behind the readout-ASIC layer are designed and fabricated. Measurement results of the main functionalities clock distribution, power cycling, and clear-pulse generation are presented. A rms-timing jitter of 2.5 ps is achieved for the distribution of an 800-MHz ±290-mV clock signal. A settling time of 10 μs and a ripple in the millivolt range are achieved for 10-Hz cycling of the 1.2-V ASIC-power nets at a load current of 2.9 A. The feasibility of 600-μs long trains containing 60-ns FWHM pulses with 10-ns rise and fall times at a repetition rate of 4.5MHz is demonstrated. Low and high levels are adjustable between 2V and 22.5V for a 2.5-Ω∥3.6-nF load.