Optimal filtering algorithm implementation in FPGAs for the ATLAS TileCal Read-Out drivers

TileCal is the hadronic calorimeter of the ATLAS experiment in the LHC (CERN). Its Read-Out Drivers (RODs) process, in real time, the digitized information coming from the front-end electronics and send it to the Read-Out System. Data processing in the ROD boards is performed in Processing Unit Mezzanine Cards that use commercial DSPs to run the Optimal Filtering (OF) algorithms. Present-day FPGAs contain dedicated hardware DSP blocks, giving the designers the possibility to implement these algorithms in a very efficient way while exploiting the flexibility that these devices provide. A prototype of a FPGA-based Processing Unit mezzanine card has been developed to perform studies about the implementation of the Optimal Filtering algorithm in a low cost FPGA. This prototype has been designed to be fully compatible with the present-system, but is also suitable for studying the possibilities of providing extended functionalities.