8-bit 5-MS/s per-pixel ADC in an 8-by-8 Matrix

A single-slope 8-bit 5-MS/s Wilkinson-type analog-to-digital converter for the DSSC mega-pixel X-ray imager was designed. Due to its simplicity, low power consumption, and small area requirement this type of ADC is suitable for pixel-level implementations. 625-ps time stamps are generated globally by means of an 8-bit Gray-code counter. They are distributed column-wise to the pixel blocks together with a conversion-start signal along 13-mm long transmission lines. The analog input voltage is sampled-and-held on a capacitor. A pixel-internal current source is used to generate a voltage ramp. The conversion into a digital word is done when the ramp voltage equals the reference voltage, and the corresponding time stamp is latched. The final readout chip will be a 64-by-64 pixel matrix. The chip prototype comprises an 8-by-8 ADC matrix representing a single 64-pixel column of the final matrix. It is fabricated in the IBM 8M1P 130-nm CMOS technology. Linearity, noise, and temperature- dependent effects are evaluated. Measurements demonstrate the achievement of a signal-to-noise ratio of 67 dB, a mean DNL of less than 0.3 LSB, and an INL below 0.5 LSB for the 5-MHz sampling rate. The area and power dissipation of the ADC's pixel circuitry amounts to 0.0139 mm² and 634 μW, respectively. The global blocks require an area of 0.0143 mm², and consume a mean power of 3.07 mW.