Evolution of the design of a second generation FireWire based data acquisition system

Developing new detector designs for PET and SPECT imaging systems often leads to problems in adapting existing data acquisition electronics to the requirements for the new devices. As we developed depth-of-interaction detector designs based on both discrete crystal arrays (dMiCE) and monolithic crystals (cMiCE) concepts, we found that our previous electronics design was inadequate to the task and launched a design effort we have termed our Phase II electronics. The system is based on a basic card design (the Phase II board) that has a large field programmable gate array (FPGA) with sufficient static RAM to support a variety of pulse processing algorithms our group has developed - including timing estimation, pulse integration with pileup correction, and statistical estimation of the event location in the detector. The Phase II board can be configured to take on several roles, including a master/coincidence controller, an acquisition node handling up to 64 channels of analog data digitized at 65 MHz and one channel digitized at >;300 MHz, an acquisition node supporting up to 64 serial data inputs (e.g., from devices like digital silicon photomultipliers), or as an acquisition node that takes in data from other Phase II boards in a star configuration to expand the number of detector modules the system can support. The current implementation is based on FireWire (limiting the total number of acquisition nodes directly connect to the bus to 62), but future versions are planned to support USB and PCIexpress. Here we report on the testing of the first prototype Phase II main board supporting a 64 channel cMiCE detector and describe the current development plans for the system.