Optimized built-in self-test technique for CAEN-based nanofabric systems

We propose a built-in self-test (BIST) technique for testing and diagnosis of molecular electronic based nanofabrics. The nanofabric architectures are reconfigurable in nature thus making it possible to utilize general methods similar to those employed for testing of FPGAs. However, a high defect rate in nanofabrics renders the traditional techniques ill-suited. Moreover, the nanoblocks offer potential for using a partially damaged nanoblock due to inherent redundancy of the architecture. This paper presents the design and analysis of testing configurations and optimization scheme that minimizes testing time while improving the utilization of the nanofabric. The proposed procedure identifies the defective nanoblocks in a nanofabric and generates a defect map, which can be used during design to avoid defective components in a nanofabric to increase the yield. The proposed BIST technique results in a less number of test configurations compared to other proposed methods and a significant reduction in the test time. This technique is suitable for architectures with a defect rate as high as 10% since all the components are tested in parallel.