A 1.0 GS/s 7bit Pipelined-Folding-Interpolating ADC with 6.0 ENOB at nyquist frequency

A single-channel 1.0 GS/s 7bit Pipelined-Folding-Interpolating analog-to-digital converter (PL-FAI-ADC) is presented. A fine and coarse joint encoding method is proposed to simplify the analog preprocessing of the coarse sub-ADC and to save power and chip area. Double-diode bootstrapped interstage switch is adopted to improve the overall efficiency of speed. The ADC implemented in 0.13-μm CMOS achieves SNDR of 37.89 dB and SFDR of 45.89 dB for 498MHz input frequency located at 1.0GS/s. The power consumption is 110mW with sampling rate of 1.0GS/s and supply voltage of 1.5/2.5 V.